Semiconductor devices have various wires for transmitting signals. For example, semiconductor devices including a transistor have a gate line, a bit line, and other wires. Meanwhile, non-volatile cross-point memory devices may include a plurality of first wires that are formed at equal intervals from each other and a plurality of second wires that may also be formed at equal intervals from each other and cross the first wires.
The widths of the wires have been constantly decreased to achieve a higher integration of devices. Accordingly, the wires may be easily bent or broken as the widths of the wires become smaller (e.g., to tens of nanometers) because the effect of surface tension on the wires largely increases. As the effect of surface tension increases, a great stress may be applied to a certain region of the wires and the wires may be bent or broken.
FIGS. 1A and 1B are scanning electron microscopic (SEM) images showing some of the problems of the conventional techniques.
FIG. 1A shows a gate line 20, having a width of approximately 50 nm, that is bent. FIG. 1B shows a wire 40 having a width of approximately 50 nm, that is cut or broken in the middle. Reference numerals 10, 30a, and 30b denote respectively a substrate, a first impurity region, and a second impurity region.
As a result, nano wires and semiconductor devices having the nano wires cannot be easily manufactured.